1. Field of the Invention
The present invention relates to the field of data processing, and more specifically to bi-directional communication registers which enable asynchronous communication between two separate logic elements.
2. Prior Art
An in-circuit emulator (ICE) is a hardware/software mechanism implemented within a micro-processor (or CPU) based integrated circuit (IC) for imitating the behavior of the IC using programming techniques and special machine features. The ICE operates in two modes of execution, an emulation mode and an interrogation mode. In emulation mode, the ICE performs real-time event evaluation during normal execution of the user code. In interrogation mode, however, normal system functions of the IC are interrupted and the ICE communicates with an external emulator system having digital logic means to interrogate the IC for register values and to execute debugging micro-code (known as a "monitor") written for testing of the IC.
To exit from emulation mode into interrogation mode, break logic is implemented to interrupt the processor's current stream of instructions. Co-pending patent application Ser. No. 07/985,563 describes an ICE apparatus for controlling a number of on-chip break mechanisms externally using a dedicated input pin. The ICE includes an instruction pointer counter and break logic connected to the instruction pointer having an arm input and being capable of matching the instruction pointer to an instruction execution address. Once a cluster is armed by a sequencer, a match from the instruction pointer matches results in a break and the emulation mode stops immediately so as to place the IC into the interrogation mode.
In order to begin interrogation of the IC, the external emulator system needs to be notified that the CPU has accepted an interrupt issued by the break logic and has ceased execution of the user code. However, the CPU and the external system run on different clocks such that their timing operations are asynchronous with respect to each other. Therefore, it would be desirable to provide an asynchronous, bi-directional communication means whereby an external system can request an interrupt to the CPU and the CPU can immediately acknowledge that the interrupt has been accepted so as to begin a non-CPU operation such as interrogation of the IC by the external system.
It is therefore an object of the present invention to provide a bi-directional communications register in a CPU-based IC that can be polled by the CPU at the same time an external system is asynchronously writing an interrupt request to the register.
It is another object of the present invention to provide a bi-directional communications register in a CPU-based IC which stores an interrupt request received from an external system and allows the CPU to asynchronously overwrite the request with an interrupt acknowledgment upon ceasing CPU operations to memory.
It is a further object of the present invention to provide the above-described bi-directional communications register in a CPU-based IC having an in circuit emulator coupled to an external emulator system for interrogating and testing the IC, the register enabling asynchronous transmission of interrupt signals between the CPU and the external system for causing transitions between emulation and interrogation modes of the IC.
It is yet a further object of the present invention to implement the above-described register in a CPU-based IC in a manner that enables serial transmission of data between the IC and an external system so as to minimize the number of IC connection pins required to effect transitions between operating modes of the IC.